Reference is made to FIG. 1 which illustrates the schematic of a simplified cyclic digital-to-analog converter (DAC) 10. The DAC 10 includes a voltage source 12. A switch 14 includes a first terminal connected to the positive terminal of the voltage source 12 and a second terminal connected to the negative terminal of the voltage source 12. The switch 14 further includes a third terminal. The switch 14 operates to selectively connect either the first terminal or second terminal to the third terminal. A switch 16 includes a first terminal connected to the third terminal of switch 14 and also includes a second terminal. The switch 16 operates to selectively connect its first terminal to its second terminal. A first capacitor 18, referred to in the art as the sampling or charging capacitor, is connected between the second terminal of switch 16 and ground. A switch 20 includes a first terminal connected to the second terminal of switch 16 (as well as a first plate of the capacitor 18) and also includes a second terminal. The switch 20 operates to selectively connect its first terminal to its second terminal. A second capacitor 22, referred to in the art as the integrating or holding or sharing capacitor, is connected between the second terminal of switch 20 and ground. Output from the circuit is taken from the second terminal of the switch 20 (at the first plate of the capacitor 22).
The operation of the DAC 10 is well known to those skilled in the art. During a first phase, switch 16 is closed and switch 14 selects either the positive terminal of the voltage source 12 or the negative terminal of the voltage source 12 based on the state of a bit of a digital word to be converted. So, for example, if the bit of the digital word is “1” the switch 14 would select the positive terminal of the voltage source 12, while if the bit of the digital word is “0” the switch 14 would select the negative terminal of the voltage source 12. This effectively samples the voltage of supply 12 corresponding to “1” or “0” (for example, Vdd or ground) at the first (sampling) capacitor 18. During a second phase, switch 16 is opened and switch 20 is closed. Charge is then shared between the first (sampling) capacitor 18 and the second (holding) capacitor 22. The process then repeats for the next bit digital word to be converted. The conversion operation typically starts with the least significant bit (LSB) of the digital word to be converted and ends with the most significant bit (MSB) of the digital word to be converted. The voltage stored on the second (holding) capacitor after processing the MSB is the converted analog output from the DAC 10 corresponding to the input digital word.
The greatest source of error in the operation of the DAC 10 is mismatch between the first (sampling) capacitor 18 and the second (holding) capacitor 22. Ideally, the first (sampling) capacitor 18 and the second (holding) capacitor 22 should have identical capacitance values. However, it is very difficult to ensure identical capacitances, and where there is a mismatch in capacitance values there is a limit on the number of bits in the digital word that can be effectively and accurately converted. A need exists in the art to address the foregoing problem.